Add-compare-select-offset device and method in a decoder

ABSTRACT

An add-compare-select-offset device including first and second adders for generating values a and b respectively equal to the sum of first previous state and branch metrics and to the sum of second previous state and branch metrics, a calculation block for providing the greatest of values a and b on a first output and generating an adjustment value on a second output; and, a third adder for generating a current state metric equal to the sum of the outputs of the calculation block, wherein the adders perform additions without keeping the carry so that the current state metric and intermediary values a and b comprise the same number of bits as the first and second previous state metrics.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to signal decoders, likefor example decoders of turbodecoder type. More specifically, thepresent invention relates to units used in such decoders, generallycalled ACSO (“Add-Compare-Select-Offset”) units, which perform additionsto provide a plurality of data, then comparisons of the obtained dataand a selection of one among the obtained data and offsets of theselected datum.

[0003] 2. Discussion of the Related Art

[0004] One the aims of digital communications is faultless datatransmission. During transmission, the data are submitted to noise,which may cause errors on the received data. To improve the reliabilityupon data transmission, error-correction techniques are used. A knownerror correction technique is the convolution coding. This techniqueprovides an efficient error correction but requires sophisticateddecoding techniques.

[0005] Error correction codes have a significant technical effect sincethey enable error correction on data transmitted between a transmitterand a receiver in applications such as telecommunications.

[0006] Convolution codes enable the digital data receiver to properlydetermine the transmitted data even when errors have occurred duringtransmission. Convolution codes introduce redundancies in the data to betransmitted and sequentially provide the transmitted data in packets inwhich the value of each bit depends on previous bits in the sequence.Thus, when errors occur, the receiver can deduce the original data byretracing the possible sequences of received data.

[0007] To improve the coding efficiency, coding methods compriseinterleavers, which mix the bit order of the coded packet. Thus, whenadjacent bits are altered during transmission, the error is distributedover the entire initial packet and can thus be more efficientlycorrected.

[0008] Other improvements may comprise coders which code the data to betransmitted more than once, in parallel or in series. For example, errorcorrection methods are known which transmit coded data packets for whicheach packet is formed by the juxta-position of initial uncoded data, offirst coded data resulting from a coding of the initial data by a firstcoder, and of second coded data resulting from a coding of the initialdata by a second coder preceded by an interleaver. Such an errorcorrection method is called a systematic parallel convolutional coding(SPCC). Each transmitted data packet may correspond to a single bit ofthe initial data, and the coding is then said to be in monobinary mode;or correspond to a couple of bits (or “bibit”) of the initial data, andthe coding is then said to be in duobinary mode.

[0009] It is known to decode by “turbodecoding” data coded in monobinarymode with an iterative algorithm, relatively efficient to achieve lowerror rates. Rather than immediately determining whether the receiveddata are equal to “0” or to “1”, the receiver assigns to each receiveddatum a value on a scale with several levels representing theprobability for the datum to be equal to “1”. A conventional scale,usually called the log likelihood ratio LLR, represents each decodeddatum x with an integer coded over a predetermined number of bits. For areceived datum r, ratio LLR is determined as follows: $\begin{matrix}{{{LLR}(x)} = {\log \left( \frac{\Pr \left( {x = {1/r}} \right)}{\Pr \left( {x = {0/r}} \right)} \right)}} & (1)\end{matrix}$

[0010] where Pr(x=1/r) represents the probability for decoded datum x tobe equal to “1” for the received datum r and Pr(x=0/r) represents theprobability for decoded datum x to be equal to “0” for the receiveddatum r.

[0011] The iterative decoding method receives an input sequencecorresponding to probabilities for each received value and outputscorrected probabilities. The iterative decoding is performed by severaliterations after which the corrected probability sufficiently closelyrepresents the transmitted datum.

[0012] The value of ratio LLR is then compared with a threshold todetermine the value of decoded datum x. For example, the decoded datumis taken to be equal to “1” when ratio LLR is positive and to “0”otherwise. Ratio LLR thus contains both information representative ofthe value of decoded datum x and information representative of thereliability of the value of the decoded datum.

[0013] The calculation algorithm of ratio LLR is based on a latticesimilar to that used in the Viterbi algorithm.

[0014]FIG. 1 shows an example of a lattice with N states, N being equalto 4 in FIG. 1. Four states S_(i), i ranging from 1 to 4, arerepresented along the vertical direction. Different times k, k rangingfrom 1 to 5, are shown along the horizontal direction. Each pointS_(i,k) of the lattice represents the i^(th) state at time k. A statemay represent a sequence of a determined number of bits corresponding tothe supposed state of several flip-flops of the convolution coder upontransmission. For a four-state lattice, each state may be associatedwith one of the sequences (“00”, “01”, “10”, “11”) corresponding to thesupposed state of two flip-flops of the coder. A branch B represents atransition between a state at a time k and a state at a time k+1. Thetransition from one state to another corresponds to the reception by thedecoder of a datum corresponding to a bit of value “0” or “1”. From astate at a time k, for example, state S_(2,3), there thus are but twopossible transitions to states S_(3,4) and S_(4,4) according to whetherthe received datum is a bit of value “0” or “1”.

[0015] In practice, datum r_(k) received at a time k is an analog datum.For a lattice branch connecting state S_(i,k) to state S_(m,k+1), ametric γ_(k) of the branch corresponding to a possible transition fromstate S_(i,k) to state S_(m,k+1) is determined. The branch metriccorresponds to a distance between received datum r_(k) and datumx_(k)(S_(i,k), S_(m,k+1)) which should have been received for thebranch. It may be calculated as follows: $\begin{matrix}{{\gamma_{k}\left( {S_{i,k},S_{m,{k + 1}}} \right)} = {\exp \left\lbrack {{- \frac{1}{2\quad \sigma^{2}}}{{r_{k} - {x_{k}\left( {S_{i,k},S_{m,{k + 1}}} \right)}}}^{2}} \right\rbrack}} & (2)\end{matrix}$

[0016] where σ² is the noise variance associated with received datumr_(k) and γ_(k)(S_(i,k),S_(m,k+1))=0 if there is no branch betweenstates S_(i,k) and S_(m,k). Two categories of branch metrics can bedistinguished hereafter:

[0017] γ_(k) ²(S_(i,k),S_(m,k+1)), equal to γ_(k)(S_(i,k),S_(m,k+1)) ifthe transition from state S_(i,k) to state S_(m,k+1) corresponds to aninformation bit at the coder input equal to 1, and equal to 0 otherwise;and

[0018] γk⁰(S_(i,k),S_(m,k+1)), equal to γ_(k)(S_(i,k),S_(m,k+1)) if thetransition from state S_(i,k) to state S_(m,k+1) corresponds to aninformation bit at the coder input equal to 0, and equal to 1 otherwise.

[0019] The calculation algorithm of ratio LLR comprises three mainsteps.

[0020] At a time k, a forward probability α_(k)(S_(i,k)) of being atstate S_(i,k) is calculated for each state S_(i,k), i ranging from 1 toN, as follows: $\begin{matrix}{{\alpha_{k}\left( S_{i,k} \right)} = {\sum\limits_{ = 1}^{N}{\sum\limits_{j = 0}^{1}{{\alpha_{k - 1}\left( S_{,{k - 1}} \right)}{\gamma_{k}^{j}\left( {S_{,{k - 1}},S_{i,k}} \right)}}}}} & (3)\end{matrix}$

[0021] For each state S_(i,k), with i ranging from 1 to N, a backwardprobability β_(k)(S_(i,k)) of being at state S_(i,k) is also calculatedat time k by the following equation: $\begin{matrix}{{\beta_{k}\left( S_{i,k} \right)} = {\sum\limits_{ = 1}^{N}{\sum\limits_{j = 0}^{1}{{\beta_{k + 1}\left( S_{,{k + 1}} \right)}{\gamma_{k + 1}^{j}\left( {S_{i,k},S_{,{k + 1}}} \right)}}}}} & (4)\end{matrix}$

[0022] From these two probabilities, ratio LLR is calculated as follows:$\begin{matrix}{{{LLR}\left( x_{k} \right)} = {\log \quad \frac{\sum\limits_{{({i,})} \in {B{({k,1})}}}{{\alpha_{k - 1}\left( S_{,{k - 1}} \right)}{\gamma_{k}^{1}\left( {S_{,{k - 1}},S_{i,k}} \right)}{\beta_{k}\left( S_{i,k} \right)}}}{\sum\limits_{{({i,})} \in {B{({k,0})}}}{{\alpha_{k - 1}\left( S_{,{k - 1}} \right)}{\gamma_{k}^{0}\left( {S_{,{k - 1}},S_{i,k}} \right)}{\beta_{k}\left( S_{i,k} \right)}}}}} & (5)\end{matrix}$

[0023] where B(k,0) (respectively B(k,1)) is the set of possibletransitions from a state S_(1,k−1) to a state _(Si,k) caused by an inputdatum equal to “0” (respectively, “1”).

[0024] The calculation of ratio LLR requires calculating multiplicationsand exponential values. Such operations are difficult to implement. Forthis purpose, the following function is introduced:

MAX⁺(x, y)=ln(e ^(x) +e ^(y))=MAX(x, y)+ln(1+e ^(=|x−y|))   (6)

[0025] where term ln(1+e^(−|x−y|)) is an offset value. The offset valuemay be obtained by means of a memory, for example, a ROM, in which arememorized values of function ln(1+e^(|v|)) over a determined number ofbits for certain values |v|coded over a determined number of bits. As aresult: $\begin{matrix}\begin{matrix}{{\ln \left( {\sum\limits_{i = 0}^{N}^{x_{i}}} \right)} = {{MAX}^{+}\left( {{\ln \left( {\sum\limits_{i = 0}^{N - 1}^{x_{i}}} \right)},x_{i}} \right)}} \\{= {{MAX}^{+}\left( {{{MAX}^{+}\left( {{\ln \left( {\sum\limits_{i = 0}^{N - 2}^{x_{i}}} \right)},x_{N - 1}} \right)},x_{N}} \right)}} \\{= {\ldots = {{\underset{i \in {\lbrack{1,N}\rbrack}}{MAX}}^{+}\left( x_{i} \right)}}}\end{matrix} & (7)\end{matrix}$

[0026] The following definitions are thus introduced:

γ_(k) ⁻¹(S _(m,n) ,S _(i,k))=log(γ_(k) ¹(S _(m,n) ,S _(i,k)))

γ_(k) ⁻⁰(S _(m,n) ,S _(i,k))=log(γ_(k) ⁰(S _(m,n) ,S _(i,k)))   (8)

{overscore (α)}_(k)(S _(i,k))=log α_(k)(S _(i,k))   (9)

[0027] Term {overscore (α)}_(k)(S_(i,k)) is called the forward statemetric for state S_(i,k) or forward path metric for state S_(i,k).

{overscore (β)}_(k)(S _(i,k))=log(β_(k)(S _(i,k)))   (10)

[0028] Term {overscore (β)}_(k)(S_(i,k)) is called the backward statemetric for state S_(i,k) or backward path metric for state S_(i,k).

[0029] As a result: $\begin{matrix}{{{\overset{\_}{\alpha}}_{k}\left( S_{i,k} \right)} = {{\underset{{({i,m})} \in {B{({k,j})}}}{MAX}}^{+}\left( {{{\overset{\_}{\alpha}}_{k - 1}\left( S_{m,{k - 1}} \right)} + {\gamma_{k}^{- j}\left( {S_{m,{k - 1}},S_{i,k}} \right)}} \right)}} & (11) \\{{{\overset{\_}{\beta}}_{k - 1}\left( S_{i,{k - 1}} \right)} = {{\underset{{({m,i})} \in {B{({k,j})}}}{MAX}}^{+}\left( {{{\overset{\_}{\beta}}_{k}\left( S_{m,k} \right)} + {\gamma_{k}^{- j}\left( {S_{i,{k - 1}},S_{m,k}} \right)}} \right)}} & (12)\end{matrix}$

[0030] The expression of ratio LLR becomes: $\begin{matrix}\begin{matrix}{{{LLR}\left( x_{k} \right)} = {{{\underset{{({i,m})} \in {B{({k,1})}}}{MAX}}^{+}\left( {{{\overset{\_}{\alpha}}_{k - 1}\left( S_{m,{k - 1}} \right)} + {\gamma_{k}^{- 1}\left( {S_{m,{k - 1}},S_{i,k}} \right)} + {{\overset{\_}{\beta}}_{k}\left( S_{i,k} \right)}} \right)} -}} \\{{{\underset{{({i,m})} \in {B{({k,0})}}}{MAX}}^{+}\left( {{{\overset{\_}{\alpha}}_{k - 1}\left( S_{m,{k - 1}} \right)} + {\gamma_{k}^{- 0}\left( {S_{m,{k - 1}},S_{i,k}} \right)} + {{\overset{\_}{\beta}}_{k}\left( S_{i,k} \right)}} \right)}}\end{matrix} & (13)\end{matrix}$

[0031] The calculations of forward metric {overscore (α)}_(k)(S_(i,k))and backward metric {overscore (β)}_(k)(S_(i,k)) are performed byspecific units of the decoder called ACSO (“ADD-COMPARE-SELECT-OFFSET)units that implement function MAX⁺.

[0032] The iterative operation of an ACSO unit implies forming severalaccumulations of a large number of sums of state and branch metricswithin a time period smaller than the period separating the reception oftwo successive bits. Such an operating speed generally implies usingredundant means in ACSO units, which makes the structure of these unitsmore complex. Further, to limit the size of the adders used foraccumulations without risking an information loss due to a saturation ofthe adders, the ACSO units comprise limiting means to, for example, whenone of the accumulations exceeds a predetermined threshold, dividing allthe accumulations by a predetermined value. Such means for limiting theaccumulations also make the structure of ACSO units complex. ACSO unitsmay also comprise means enabling compensation of a variation of thebranch metric due to a variation in the transmission gain. Such gaincompensation means have in particular the effect of increasing the sizeof the ROM in which are memorized the adjustment values, and make evenmore complex the preceding accumulation limiting means.

[0033] A coding in duobinary mode enables transmitting at an equalfrequency the data with a greater rate than a coding in monobinary mode.No simple devices are however known to implement a decoding in duobinarymode.

SUMMARY OF THE INVENTION

[0034] An object of the present invention consists of providing a simpleand low-cost device to implement a decoding in monobinary mode.

[0035] Another object of the present invention consists of providing asimple and low-cost device to implement a decoding in duobinary mode.

[0036] To achieve these and other objects, the present inventionprovides a device for implementing a function ofadd-compare-select-offset type in an error-correction code decoder,comprising:

[0037] first and second adders for generating first and secondintermediary metric values a and b respectively equal to the sum of afirst previous state metric and of an associated branch metric and tothe sum of a second previous state metric and of an associated branchmetric;

[0038] a calculation block receiving values a and b, to compare values aand b, select the greatest of values a and b and provide said selectedvalue on a first output, and to generate on a second output anadjustment value corresponding to an approximation of ln(1+e^(−|a−b|));and

[0039] a third adder for generating a current state metric equal to thesum of the outputs of the calculation block;

[0040] wherein the first and second previous state metrics are codedover a same number of bits, and wherein the adders perform additionswithout keeping the carry so that the current state metric andintermediary values a and b comprise the same number of bits as thefirst and second previous state metrics.

[0041] The present invention also aims at a device for implementing afunction of add-compare-select-offset type in an error-correction codedecoder operating in duobinary mode, comprising:

[0042] first and second devices such as described hereabove respectivelycomprising first and second calculation blocks for generating first andsecond current state metrics respectively from first and second previousstate metrics and first and second associated branch metrics and fromthird and fourth previous state metrics and third and fourth associatedbranch metrics;

[0043] a third calculation block such as described hereabove receivingas an input the first and second current state metrics; and

[0044] an adder for generating a third current state metric equal to thesum of the outputs of the third calculation block, in which the previousstate metrics are each coded over a same number of bits, said adderperforming additions without keeping the carry so that the third currentstate metric comprises the same number of bits as the previous statemetrics.

[0045] According to an embodiment of the present invention, thecalculation block comprises a subtractor for calculating the differenceof the first and second values received by the calculation block, amultiplexer controlled by the output of the subtractor to generate onthe first output of the calculation block the largest of the receivedvalues, and an approximation block for generating on the second outputof the calculation block the adjustment value in the form of a value ofone bit equal to 1 if said difference is equal to 0, 1, or −1, and equalto 0 otherwise.

[0046] According to an embodiment of the present invention, theapproximation block comprises a first logic gate calculating a NOR ofall the bits of said difference except for its least significant bit, asecond logic gate calculating an AND of all the bits of said difference,and a third logic gate calculating an OR of the outputs of the first andsecond logic gates.

[0047] The present invention also aims at a decoder comprising 2^(N),where N is greater than 1, devices in duobinary mode such as describedhereabove, each of which is associated with a specific N bit value, thedecoder receiving data in the form of consecutive bibits;

[0048] the output of each device associated with a first value beingconnected to provide one of the previous state metrics to four devices,each associated with a value, the N−2 most significant bits of which arethe N−2 least significant bits of said first value and the two leastsignificant bits of which respectively are one of the four possiblevalues of the last received bibit;

[0049] each device associated with a first value, the two leastsignificant bits of which are one of the four possible values (00, 01,10, 11) of a bibit receiving as branch metrics a value corresponding toa distance between the received bibit and said one of the four possiblevalues of a bibit.

[0050] The present invention also aims at a method for implementing afunction of add-compare-select-offset type in an error-correction codedecoder operating in monobinary mode, comprising the steps of:

[0051] i/ generating first and second intermediary metrics values, a andb, respectively equal to the sum of a first previous state metric and ofan associated branch metric and to the sum of a second previous statemetric and of an associated branch metric;

[0052] ii/ comparing values a and b, selecting the largest of values aand b, and providing said selected value on a first output, andgenerating on a second output an adjustment value corresponding to anapproximation of ln(1+e^(−|a−b|)); and

[0053] iii/ generating a current state metric equal to the sum of theoutputs of the calculation block;

[0054] the first and second previous state metrics being coded over asame number of bits and the sums calculated at steps i/ and iii/ beingperformed without keeping the carry, so that the current state metricand intermediary values a and b comprise the same number of bits as thefirst and second previous state metrics.

[0055] The present invention also aims at a method for implementing afunction of add-compare-select-offset type in an error-correction codedecoder operating in duobinary mode, comprising the steps of:

[0056] iv/ generating first and second current state metric according tothe previously-described method in monobinary mode, respectively fromfirst and second previous state metrics and from first and secondassociated branch metrics and from third and fourth previous statemetrics and from third and fourth associated branch metrics;

[0057] v/ providing a selected value and an approximation valuecalculated according to step ii/ of the previously-described method inmonobinary mode, based on the first and second current state metric; and

[0058] vi/ generating a third current state metrics equal to the sum ofthe values generated at step v/, the previous state metric being eachcoded over a same number of bits and said sum being calculated withoutkeeping the carry so that the third current state metric comprises thesame number of bits as the previous state metrics.

[0059] According to an embodiment of the present invention, at step ii/,the value is selected by calculating the difference of the comparedvalues and by providing the largest of the compared values based on thesign of said difference, and the adjustment value is generated as beinga value of one bit equal to I if said difference is equal to 0, 1, or−1, and equal to 0 otherwise.

[0060] According to an embodiment of the present invention, theadjustment value is equal to the logic OR of a logic NOR of all the bitsof said difference except for its least significant bit and of a logicAND of all the bits of said difference.

[0061] The present invention also aims at a method for decoding in alattice comprising 2^(N), where N is greater than 1, states eachassociated with a specific N-bit value, data received in the form ofconsecutive bibits, comprising the steps of:

[0062] vii/ for the first received bibit, generating according to thepreviously-described decoding method in duobinary mode 2^(N) currentstate metrics each associated with one of said values based on fourpredetermined initial previous state metrics and based on four identicalbranch metric corresponding to a distance between the received bibit anda value of the bibit equal to the two least significant bits of said oneof said values;

[0063] viii/ for each subsequently received bibit, generating accordingto the previously-described decoding method in duobinary mode 2^(N)current state metric each associated with one of said values, taking forthe four previous state metrics the four current state metrics generatedfor the previous received bibit and associated with a value, the N−2least significant bits of which are the N−2 most significant bits ofsaid one of said values, and taking for the four branch metrics adistance between the received bibit and a value of the bibit equal tothe two least significant bits of said one of said values.

[0064] The foregoing objects, features, and advantages of the presentinvention will be discussed in detail in the following non-limitingdescription of specific embodiments in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0065]FIG. 1, previously described, shows an example of a lattice usedfor a monobinary decoding;

[0066]FIG. 2 shows an example of a lattice used for a duobinary decodingaccording to the present invention;

[0067]FIG. 3 shows an embodiment of an ACSO unit according to thepresent invention; and

[0068]FIG. 4 shows an example of a decoding circuit corresponding to thelattice of FIG. 2 using ACSO units such as in FIG. 3.

DETAILED DESCRIPTION

[0069]FIG. 2 shows an example of a lattice for decoding data coded induobinary mode. The lattice comprises 5 columns, each comprising 8states S_(i,j), where i=1-8 and j=1-5. Each column is associated with adifferent time corresponding to the reception of a new data bibit. Foran eight-state lattice, each state may be associated with one of thesequences (“000”, “001”, “010”, “011”, “100”, “101”, “110”, “111”) ofthe internal states of the convolution coder. From each state at a timek (for example, state S_(2,3)), there are four possible transitions (inthe considered example towards states S_(5,4), S_(6,4), S_(7,4), andS_(8,4,) according to whether the received bibit has a value “00”, “01”,“10”, or “11”).

[0070] In practice, like for a decoding in monobinary mode, atransmitted bibit is received at each time k in the form of an analogdatum, and with each branch of the lattice is associated a branch metricγ_(k) calculated substantially in the same way as according to thepreceding equation (2), calling r_(k) the received analog value andx_(k) the bibit which should have been received for the branch, or“received bibit”.

[0071] Four categories of branch metrics are distinguished hereafter:

[0072] γ_(k) ⁰⁰(S_(i,k),S_(m,k+1)), equal to γ_(k)(S_(i,k),S_(m,k+1)) ifthe transition from state S_(i,k) to state S_(m,k+1) corresponds to aninformation bibit at the coder input equal to 00, and equal to 0otherwise;

[0073] γ_(k) ⁰¹(S_(i,k),S_(m,k+1)), equal to γ_(k)(S_(i,k),S_(m,k+1)) ifthe transition from state S_(i,k) to state S_(m,k+1) corresponds to aninformation bibit at the coder input equal to 01, and equal to 1otherwise;

[0074] γ_(k) ¹⁰(S_(i,k),S_(m,k+1)), equal to γ_(k)(S_(i,k),S_(m,k+1)) ifthe transition from state S_(i,k) to state S_(m,k+1) corresponds to aninformation bibit at the coder input equal to 10, and equal to 0otherwise;

[0075] γ_(k) ¹¹(S_(i,k),S_(m,k+1)), equal to γ_(k)(S_(i,k),S_(m,k+1)) ifthe transition from state S_(i,k) to state S_(m,k+1) corresponds to aninformation bibit at the coder input equal to 11, and equal to 1otherwise.

[0076] The present inventors have shown that it is possible, forexample, by following a lattice such as in FIG. 2, to measure at eachtime the probability for the received bibit to have one of the fourpossible values, by means of four ratios LLR each calculated as follows:$\begin{matrix}\begin{matrix}{{{LLR}_{00}\left( x_{k} \right)} = {{\underset{{({i,m})} \in {B{({k,00})}}}{MAX}}^{+}\left( {{{\overset{\_}{\alpha}}_{k - 1}\left( S_{m,{k - 1}} \right)} + {\gamma_{k}^{- 00}\left( {S_{m,{k - 1}},S_{i,k}} \right)} + {{\overset{\_}{\beta}}_{k}\left( S_{i,k} \right)}} \right)}} \\{{{LLR}_{01}\left( x_{k} \right)} = {{\underset{{({i,m})} \in {B{({k,01})}}}{MAX}}^{+}\left( {{{\overset{\_}{\alpha}}_{k - 1}\left( S_{m,{k - 1}} \right)} + {\gamma_{k}^{- 01}\left( {S_{m,{k - 1}},S_{i,k}} \right)} + {{\overset{\_}{\beta}}_{k}\left( S_{i,k} \right)}} \right)}} \\{{{LLR}_{10}\left( x_{k} \right)} = {{\underset{{({i,m})} \in {B{({k,10})}}}{MAX}}^{+}\left( {{{\overset{\_}{\alpha}}_{k - 1}\left( S_{m,{k - 1}} \right)} + {\gamma_{k}^{- 10}\left( {S_{m,{k - 1}},S_{i,k}} \right)} + {{\overset{\_}{\beta}}_{k}\left( S_{i,k} \right)}} \right)}} \\{{{LLR}_{11}\left( x_{k} \right)} = {{\underset{{({i,m})} \in {B{({k,11})}}}{MAX}}^{+}\left( {{{\overset{\_}{\alpha}}_{k - 1}\left( S_{m,{k - 1}} \right)} + {\gamma_{k}^{- 11}\left( {S_{m,{k - 1}},S_{i,k}} \right)} + {{\overset{\_}{\beta}}_{k}\left( S_{i,k} \right)}} \right)}}\end{matrix} & (14)\end{matrix}$

[0077] where B(k,00) (respectively B(k,01), B(k,10), B(k,11)) is the setof all possible transitions from a state S_(m,k−1) to a state S_(i,k)caused by an input bibit equal to “00” (respectively “01”, “10”, “11”).

[0078] The decoding is performed by comparing the calculated LLRs:

[0079] if MAX(LLR₀₀(x_(k)), LLR₀₁(x_(k)), LLR₁₀(x_(k)),LLR₁₁(x_(k)))=LLR₀₀(x_(k)), the decoded bibit is 00;

[0080] if MAX(LLR₀₀(x_(k)), LLR₀₁(x_(k)), LLR₁₀(x_(k)),LLR₁₁(x_(k)))=LLR₀₁(x_(k)), the decoded bibit is 01;

[0081] if MAX(LLR₀₀(x_(k)), LLR₀₁(x_(k)), LLR₁₀(x_(k)),LLR₁₁(x_(k)))=LLR₁₀(x_(k)), the decoded bibit is 10;

[0082] if MAX(LLR₀₀(x_(k)), LLR₀₁(x_(k)), LLR₁₀(x_(k)),LLR₁₁(x_(k)))=LLR₁₁(x_(k)), the decoded bibit is 11.

[0083] Values {overscore (α)}_(k−1), {overscore (β)}_(k) arerespectively calculated according to previous equations (9) and (10),with α_(k)(S_(i,k)), which is the forward probability of being at stateS_(i,k,) equal to: $\begin{matrix}{{\alpha_{k}\left( S_{i,k} \right)} = {\sum\limits_{ = 1}^{N}{\sum\limits_{{j = 00},01,10,11}^{3}{{\alpha_{k - 1}\left( S_{,{k - 1}} \right)}{\gamma_{k}^{j}\left( {S_{,{k - 1}},S_{i,k}} \right)}}}}} & (15)\end{matrix}$

[0084] and β_(k)(S_(i,k)), which is the backward probability of being atstate S_(i,k,) equal to: $\begin{matrix}{{\beta_{k}\left( S_{i,k} \right)} = {\sum\limits_{l = 1}^{N}\quad {\sum\limits_{{j = 00},01,10,11}^{3}\quad {{\beta_{k + 1}\left( S_{l,{k + 1}} \right)}{\gamma_{k + 1}^{j}\left( {S_{i,k},S_{l,{k + 1}}} \right)}}}}} & (16)\end{matrix}$

[0085] The present inventors have in particular shown that:$\begin{matrix}{{{\overset{\_}{\alpha}}_{k}\left( S_{i,k} \right)} = {{MAX}^{+}\left( {{MAX}^{+}\left( {{{{\overset{\_}{\alpha}}_{k - 1}\left( S_{{m1},{k - 1}} \right)} + {\gamma_{k}^{- 00}\left( {S_{{m1},{k - 1}},S_{i,k}} \right)}},} \right.} \right.}} & (17) \\{\quad {\left( {{{\overset{\_}{\alpha}}_{k - 1}\left( S_{{m2},{k - 1}} \right)} + {\gamma_{k}^{- 01}\left( {S_{{m2},{k - 1}},S_{i,k}} \right)}} \right),}} & \quad \\{\quad {{MAX}^{+}\left( {{{{\overset{\_}{\alpha}}_{k - 1}\left( S_{{m3},{k - 1}} \right)} + {\gamma_{k}^{- 10}\left( {S_{{m3},{k - 1}},S_{i,k}} \right)}},} \right.}} & \quad \\\left. \quad \left( {{{\overset{\_}{\alpha}}_{k - 1}\left( S_{{m4},{k - 1}} \right)} + {\gamma_{k}^{- 11}\left( {S_{{m4},{k - 1}},S_{i,k}} \right)}} \right) \right) & \quad \\{{and}\quad {that}\text{:}} & \quad \\{{{\overset{\_}{\beta}}_{k}\left( S_{i,{k - 1}} \right)} = {{MAX}^{+}\left( {{MAX}^{+}\left( {{{{\overset{\_}{\beta}}_{k}\left( S_{{m1},k} \right)} + {\gamma_{k}^{- 00}\left( {S_{i,{k - 1}},S_{{m1},k}} \right)}},} \right.} \right.}} & (18) \\{\quad {\left( {{{\overset{\_}{\beta}}_{k}\left( S_{{m2},k} \right)} + {\gamma_{k}^{- 01}\left( {S_{i,{k - 1}},S_{{m2},k}} \right)}} \right),}} & \quad \\{\quad {{MAX}^{+}\left( {{{{\overset{\_}{\beta}}_{k}\left( S_{{m3},k} \right)} + {\gamma_{k}^{- 10}\left( {S_{i,{k - 1}},S_{{m3},k}} \right)}},} \right.}} & \quad \\\left. \quad \left( {{{\overset{\_}{\beta}}_{k}\left( S_{{m4},k} \right)} + {\gamma_{k}^{- 11}\left( {S_{i,{k - 1}},S_{{m4},k}} \right)}} \right) \right) & \quad\end{matrix}$

[0086] with Sm1, Sm2, Sm3, Sm4 being the states preceding state Si (inthe case of the calculation of α, and following state Si in the case ofthe calculation of β) for transitions respectively due to input bibits00, 01, 10, and 11.

[0087] Above formulas (17) and (18) result in that each of forward andbackward state metrics {overscore (α)}_(k)(S_(i,k)) and {overscore(β)}_(k)(S_(i,k)) can be calculated by an ACSO unit in duobinary modeaccording to the present invention, comprising two ACSO units inmonobinary mode, each calculating the MAX⁺ of two sums of a state metricand of an associated branch metric, followed by a block calculating theMAX⁺ of the results of the ACSO units in monobinary mode.

[0088]FIG. 3 shows an ACSO unit in duobinary mode MM1 according to thepresent invention, enabling calculation of the state metric (forward andbackward) of a considered state at a given time k. Hereafter, term“state metric” is indifferently used for a forward state metric and fora backward state metric and, when reference is made to a state adjacentto the considered state, this means a state at a time subsequent k+1 orprior k−1 to the considered state, according to the considered metric.

[0089] The ACSO unit in duobinary mode DM comprises a first ACSO unit inmonobinary mode MM1. Unit MM1 receives as an input data MI₁, MI₂, whichrespectively represent the first and second previous state metrics. UnitMM1 also receives data GI₁, GI₂, which represent branch metricscorresponding to the branches between the considered state and,respectively, the first and second adjacent states. Unit MM1 comprisestwo adders 10 and 11 respectively receiving as an input data MI₁, GI₁,and MI₂, GI₂. A calculation block 12 receives, on two inputs, values(a,b) output by adders 10 and 11. Calculation block 12 comprises asubtractor 13 calculating difference a−b. A multiplexer 14 receivingvalues a and b provides MAX1=MAX(a,b), that is, either value a or valueb according to whether difference a−b is positive or negative (accordingto whether the sign bit of a−b is equal to 0 or 1). An approximationblock 15 receives difference a−b and provides a value ADJ1 equal to 1 ifdifference a−b has a value equal to 0, 1, or −1, and a value equal to 0otherwise. Value ADJ1 is shown to be an approximation coded over 1 bitof adjustment value ln(1+e^(−|a−b|)). Block 15 for example comprises alogic gate 16 calculating a NOR of all the bits of difference a−b exceptfor its least significant bit, a logic gate 17 calculating an AND of allthe bits of difference a−b, and a logic gate 18 calculating an OR of theoutputs of gates 16 and 17. An adder 19 provides sum MAXP1 of valuesMAX1 and ADJ1, where MAXP1=MAX⁺(a,b) in compliance with formula (6).

[0090] Duobinary ACSO unit DM comprises a second monobinary ACSO unitMM2 of same structure as unit MM1, generating a current state metricMAXP2 based on data MI₃, MI₄, GI₃, and GI₄ respectively representing thethird and fourth previous state metrics and corresponding branchmetrics. Same reference numerals in which the 1 of the ten's place hasbeen replaced with a 2 refer to same elements in units MM1 and MM2.

[0091] Duobinary ACSO unit DM also comprises a calculation block 32 ofsame structure as calculation block 12 of unit MM1. Same referencenumerals in which the 1 of the tens has been replaced with a 3 refer tosame elements in blocks 12 and 32. Block 32 receives outputs MAXP1 andMAXP2 of units MM1 and MM2 and provides an adder 39 with a value MAX3equal to the maximum of MAXP1 and MAXP2 and an adjustment value ADJ3corresponding to ln(1+e^(−|MAXP1−MAXP2|)). Output MAXP3 of adder 39forms the output of unit DM. Unit DM operates preferably synchronously,and comprises data synchronization means not shown such as D flip-flops.Unit DM also preferably comprises reset means not shown, for example,enabling controllably setting back to 0 the outputs of adders 10 and 11of unit MM1 and the corresponding adders of unit MM2.

[0092] The present inventors have shown that the performances of adecoder using a monobinary ACSO unit according to the present inventionsuch as unit MM1, with a single-bit adjustment value ADJ1, are not underthe performances of a decoder using a conventional monobinary ACSO unitwith an adjustment value over several bits stored in a ROM. Indeed, adecoder comprises other systems (in particular upstream of the LLRcalculation), the operation of which is more penalizing for the decoderperformances, so that the use of a single-bit adjustment value has noinfluence on the general decoder performances. It can also be shown thata decoder using a DM unit with single-bit adjustment values ADJ1, ADJ2,and ADJ3 according to the present invention has performances which areas good as those of a decoder using a unit DM with adjustment valuesover several bits generated by means of ROMs, while having a sizesubstantially reduced by the suppression of the ROMs.

[0093] State metric values MI₁, MI₂ are coded over a same number of bitsn. According to the present invention and in particularly advantageousfashion, adders 10, 11, and 19 of unit MM1 operate modulo n withoutkeeping the carry, to each provide an output coded over the same numberof bits n. The present inventors have indeed found that uponimplementation of above formulas (17) or (18), the maximum differencebetween sum a of MI₁ and GI₁ and sum b of MI₂ and GI₂ is always smallerthan a predetermined value δ, as well as a+ADJ1−b or b+ADJ1−a. If n ischosen such that n≧2δ, the fact for the adders of unit MM1 to performadditions modulo n introduces no error in the calculation of the outputvalue of unit MM1. Similarly, the values of state metrics MI₃, MI₄ arecoded over n bits and the adders of unit MM2 as well as adder 39 operatewith no keeping of the carry, whereby the value output by unit MM1 isalso coded over n bits. Such an ACSO unit structure has the advantage ofnever being saturated while being particularly simple to implement.Further, such a structure advantageously comprises a single gaincompensation means (not shown) on its input, and not a plurality of suchmeans arranged at the level of the adders performing the accumulationsin conventional ACSO units.

[0094]FIG. 4 schematically shows an example of a circuit 40 using ACSOunits in duobinary mode according to the present invention to perform adecoding based on the lattice of FIG. 2. Circuit 40 comprises eight ACSOunits (DM0, DM1, DM2, DM3, DM4, DM5, DM6, DM7). The four state metricinputs MI₁, MI₂, MI₃, MI₄ of units DM0, DM1, DM2, and DM3 arerespectively connected to the outputs of units DM0, DM2, DM4, and DM6.The four state metric inputs MI₁, MI₂, MI₃, MI4 of units DM4, DM5, DM6,and DM7 are respectively connected to the outputs of units DM1, DM3, DM5and DM7. Units DM0, DM1, DM2, DM3, DM4, DM5, DM6, DM7 are rated by asignal not shown to provide an output value upon reception of each bit.

[0095] The four branch metric inputs GI₁, GI₂, GI₃, GI₄ of units DM0 andDM4 are connected to a block not shown providing upon reception of eachbibit a branch metric {overscore (γ)}₀₀ corresponding to the distancebetween value 00 and the value of the received bibit. Similarly, thebranch metric inputs of the units, respectively DM1 and DM5, DM2 andDM6, DM3 and DM7 receive upon reception of each bibit values {overscore(γ)}₀₁, {overscore (γ)}₁₀, {overscore (γ)}₁₁ corresponding to thedistances between values 01, 10, 11 and the value of the received bibit.

[0096] Of course, the present invention is likely to have variousalterations, modifications, and improvements which will readily occur tothose skilled in the art. In particular, each of the describedcomponents may be replaced with one or several components performing thesame function. Thus, the structures of unit MM1, of calculation block12, or of block 15 may be similar to the corresponding structuresdescribed in European patent application number 03354009.7 filed by theapplicant.

[0097] The present invention has been described in relation with adecoding according to an 8-state lattice such as in FIG. 2, but thoseskilled in the art will readily adapt the present invention to adecoding according to other 8-state lattices or according to a2^(N)-state lattice, where N is greater than 1.

[0098] Such alterations, modifications, and improvements are intended tobe part of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

What is claimed is:
 1. A device (MM4) for implementing a function ofadd-compare-select-offset type in an error-correction code decoder,comprising: first and second adders for generating first and secondintermediary metric values a and b respectively equal to the sum of afirst previous state metric and of an associated branch metric and tothe sum of a second previous state metric and of an associated branchmetric; a calculation block receiving values a and b, to compare valuesa and b, select the greatest of values a and b and provide said selectedvalue on a first output, and to generate on a second output anadjustment value corresponding to an approximation of ln(1+e^(−|a−b|));and a third adder for generating a current state metric equal to the sumof the outputs of the calculation block; wherein the first and secondprevious state metrics are coded over a same number of bits, and whereinthe adders perform additions without keeping the carry so that thecurrent state metric and intermediary values a and b comprise the samenumber of bits as the first and second previous state metrics.
 2. Adevice for implementing a function of add-compare-select-offset type inan error-correction code decoder operating in duobinary mode,comprising: first and second devices of claim 1 respectively comprisingfirst and second calculation blocks for generating first and secondcurrent state metrics respectively from first and second previous statemetrics and first and second associated branch metrics and from thirdand fourth previous state metrics and third and fourth associated branchmetrics; a third calculation block of claim 1 receiving as an input thefirst and second current state metrics; and an adder for generating athird current state metric equal to the sum of the outputs of the thirdcalculation block wherein the previous state metrics are each coded overa same number of bits, said adder performing additions without keepingthe carry so that the third current state metric comprises the samenumber of bits as the previous state metrics.
 3. The device of claim 1,wherein the calculation block comprises: a subtractor for calculatingthe difference between the first and second values received by thecalculation block; a multiplexer controlled by the output of thesubtractor to generate on the first output of the calculation block thelargest of the received values; an approximation block for generating onthe second output of the calculation block the adjustment value in theform of a value of one bit equal to 1 if said difference is equal to 0,1, or −1, and equal to 0 otherwise.
 4. The device of claim 3, whereinthe approximation block comprises a first logic gate calculating a NORof all the bits of said difference except for its least significant bit,a second logic gate calculating an AND of all the bits of saiddifference, and a third logic gate calculating an OR of the outputs ofthe first and second logic gates.
 5. A decoder comprising 2^(N), where Nis greater than 1, devices of claim 2, each of which is associated witha specific N bit value, the decoder receiving data in the form ofconsecutive bibits; the output of each device associated with a firstvalue being connected to provide one of the previous state metrics tofour devices, each associated with a value, the N−2 most significantbits of which are the N−2 least significant bits of said first value andthe two least significant bits of which respectively are one of the fourpossible values of the last received bibit; each device associated witha first value, the two least significant bits of which are one of thefour possible values of a bibit, receiving as branch metrics a valuecorresponding to a distance between the received bibit and said one ofthe four possible values of a bibit.
 6. A method for implementing afunction of add-compare-select-offset type in an error-correction codedecoder operating in monobinary mode, comprising the steps of: i/generating first and second intermediary metrics values, a and b,respectively equal to the sum of a first previous state metric and of anassociated branch metric and to the sum of a second previous statemetric and of an associated branch metric; ii/ comparing values a and b,selecting the largest of values a and b, and providing said selectedvalue on a first output, and generating on a second output an adjustmentvalue corresponding to an approximation of ln(1+e^(−|a−b|)); and iii/generating a current state metric equal to the sum of the outputs of thecalculation block; the first and second previous state metrics beingcoded over a same number of bits and the sums calculated at steps i/ andiii/ being performed without keeping the carry, so that the currentstate metric and intermediary values a and b comprise the same number ofbits as the first and second previous state metrics.
 7. A method forimplementing a function of add-compare-select-offset type in anerror-correction code decoder operating in duobinary mode, comprisingthe steps of: iv/ generating first and second current state metricsaccording to the method of claim 6, respectively from first and secondprevious state metrics and from first and second associated branchmetrics and from third and fourth previous state metric and from thirdand fourth associated branch metric; v/ providing a selected value andan approximation value calculated according to step ii/ of claim 6,based on the first and second current state metric; and vi/ generating athird current state metric equal to the sum of the values generated atstep v/, the previous state metric being each coded over a same numberof bits and said sum being calculated without keeping the carry so thatthe third current state metric comprises the same number of bits as theprevious state metrics.
 8. The method of claim 6 or 7, wherein at stepii/, the value is selected by calculating the difference of the comparedvalues and by providing the largest of the compared values based on thesign of said difference, and wherein the adjustment value is generatedas being a value of one bit equal to 1 if said difference is equal to 0,1, or −1, and equal to 0 otherwise.
 9. The device of claim 8, whereinthe adjustment value is equal to the logic OR of a logic NOR of all thebits of said difference except for its least significant bit and of alogic AND of all the bits of said difference.
 10. A decoding in alattice comprising 2^(N), where N is greater than 1, states, eachassociated with a specific N-bit value, of data received in the form ofconsecutive bibits, comprising the steps of: vii/ for the first receivedbibit, generating according to the method of claim 7 2^(N) current statemetrics each associated with one of said values based on fourpredetermined initial previous state metrics and based on four identicalbranch metrics corresponding to a distance between the received bibitand a value of the bibit equal to the two least significant bits of saidone of said values; viii/ for each subsequently received bibit,generating according the method of claim 7 2^(N) current state metricseach associated with one of said values, taking for the four previousstate metrics the four current state metrics generated for the previousreceived bibit and associated with a value, the N−2 least significantbits of which are the N−2 most significant bits of said one of saidvalues, and taking for the four branch metrics a distance between thereceived bibit and a value of the bibit equal to the two leastsignificant bits of said one of said values.